Information processing systems, which handle ever increasing amounts of data, require parallel processing devices that have the ability to handle the increasing amounts of data. The control and sequencing of the processing generally requires extensive hardware to insure that the maximum efficiency is obtained in the distribution of the data to each processing device.
It is, therefore, an object of the present invention to provide a simplified hardware for the control of the splitting and merging of a data stream through multiple parallel processing units.
Formerly, separate multiplexer and demultiplexer controlled hardware was required at each unit interface to control the distribution of each section of data into a separate processing unit. Thus a demultiplexer was required in order to distribute the data to the separate processing units and a multiplexer was needed at the exit of the processing unit in order to reassemble the data. Separate multiplexers and demultiplexers were required if the processing device was a reversible type unit such as a compactor/decompactor unit where the data was compacted through the processing unit and decompacted when the data was returned from the memory store for instance for placing the data into its original format as sent by a host central processing unit.
It is, therefore, another object of the present invention to provide hardware at the interfaces to a processing unit that can act as a distribution sequencing unit and an assembling resequencing unit, a demultiplexer and a multiplexer, to thereby lessen the hardware requirement while providing control of the splitting and merging of the data stream through the processing device.